JOB DUTIES:Responsible for RTL design of portions of high-speed GDDR, DDR, and SERDES using System Verilog/Verilog HDL for implementation and debug.Read and comprehend System on Chip level architectural specification.Write microarchitecture specification for new and modified functions. Responsible for linting, CDC checks and simulation of design.Work with synthesis and backend teams for STA and physical implementation.EDUCATION:Bachelor's or Master's in Computer Engineering
