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  • ID
    #55275354
  • Salary
    TBD
  • Source
    Rolls-Royce
  • Date
    2026-08-07
  • Deadline
    2026-10-06
 
Full-time

IN (Hybrid Work Schedule)Rolls-Royce is looking for a Principal Engineer - FPGA/ASIC Design Specialist (Field Programmable Gate Arrays / policy. All hybrid employees must have a secure, high-speed internet connection and an appropriate workspace that complies with applicable

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