Design Verification Engineer

Arizona, Phoenix, 85004

Contract

Vacancy expired!

Roles & Responsibilities:

Testbench development - System Verilog UVM and C tests
Integration/development of C tests/APIs and SW build flow
Integration/development of UVM mailboxes and HW/SW communication components
Integration of lower level UVM testbenches
Test plan development
Power Aware testbench development and simulations
Seamless porting between simulation/emulation/prototyping platforms
Regression setup and debug for RTL/Gate Level Netlist/UPF PA sim/Emulation/Proto
Coverage collection and closure
Working with cross functional teams (DV/Arch/Design/FW) to identify coverage scope

Must Have:

1 year of experience in RTL Design and Verification area of which 2+ years of
experience in SoC Design Verification and HW/SW verification or
Master Degree in relevant subject and 1 year of internship and/or verification or design specific projects
Knowledge of System Verilog UVM and vertical testbench integration
Knowledge of low level HW/SW interaction and

Note: We are fine with s as well who has done relevant projects.

verification,OVM,UVM

Vacancy expired!

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