SoC Verification Engineer

SoC Verification EngineerFull timeLocation – Dallas, TXResponsibilities:Should have understanding, knowledge and experience in “C” Programming Language. This is a must have.Should have good/decent communication skills and experience in working in a multi-member, multi-site teamShould have created test plans from specifications/requirements; written tests, performed simulations/debug of the design/test.Should have knowledge in Verilog Language. Should possess understanding of concepts such as clock/resets/power/DFT/debug/IO in an SOC Context.Should have experience in performing RTL/Power Aware RTL simulations in an SOC Context.Should have performed Gate Level Simulations (Unit Gate, Power, with and without timing)Should have knowledge and understanding about Test Vector Generation and productization of a design.Should have performed and/or have knowledge in Silicon bring up on a Validation board.Should be able to write & support scripts in a scripting language such as PERL or Python or TCL or in shell (csh/tcsh/bash)Working knowledge in core (ARM(A/M/R) or DSP) based SOC design/architecture and debug (especially using TARMAC)Understanding of Standard Cell Library (Synchronizers/clock buffers/power switches), memories is presumed.Knowledge in tools such as Cadence Xcelium/Indago/JasperShould have working knowledge of configuration tools such as Designsync, or Clearcase or RCS and database management and UNIX commands.