RESPONSIBILITIES: • Understand the architecture of the graphics IP and functional block being designed. • Verify the block through formal verification (formal property verification, sequential equivalence check (SEQ)). • Set up and run formal verification flows • Debug and fix failures • Working knowledge of various asic design verification standards and languageREQUIREMENTS: • Have in depth knowledge of pre-silicon verification for CPU / GPU blocks. • 8-10 years of asic design verification experience. • Excellent knowledge of Verilog, familiarity with System Verilog, UVM and C • Experience using industry standard tools and adaptability to utilize home grown tools. • Experience with formal verification flows. • Strong analytical/problem solving skills and pronounced attention to details. • Must be a self-starter and be able to independently drive tasks to completion. • Strong interpersonal and communication skills. • Prior experience with verification of graphics design/pipelining is a plus.Location: Can sit in either Santa Clara OR Orlando
