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  • ID
    #7262717
  • Job type
    Contract
  • Salary
    USD TBD TBD
  • Source
    Vimerse Infotech Inc
  • Date
    2020-12-23
  • Deadline
    2021-02-21

Vacancy expired!

JobTitle:Analog layout Engineer Location:Santa clara,CA mandatory : 5nm and 7nm tech Qualifications:

  • Familiarity with analog matching requirements and practice of it in layouts is a must
  • Expertise on Cadence virtuoso custom/analog layout platform
  • Knowledge of layout techniques for device matching, minimize parasitic, high speed routing.
  • Working knowledge on various analog IP blocks: PLLs, ADC, DAC, Bandgap ref and other high speed connectivity ckts.
  • Good understanding of parasitic RC delay, signal integrity and EM Deep sub-micron CMOS layout experience 16nm and smaller geometries ( Will be a + if done work using either 7nm or 5nm).
  • Good understanding of layout extractions, verification methods which includes LVS, DRC and ERC checks on leading foundry flows.
  • Chip planning and block implementation
  • Ability to estimate layout schedule for a given circuit, layout planning and provide early feedback to circuit design engineers etc.
  • Ability to work with circuit designers that are located remotely which requires the documentation skills and communication skills.
  • Skills & Experience
  • Analog Layout,Digital Physical Design at SoC Level Exp

Vacancy expired!

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