FPGA RTL Design Engineer

Vacancy expired!

FPGA RTL

Design EngineerWe have the below full time position with our client in San Jose. Pls send your resume with your salary expectation.

DESIRED SKILLS AND EXPERIENCE

• Experience in Logic design / micro-architecture / RTL coding is required.
• Expertise in Verilog is a must.
• Should have knowledge of AMBA protocols - AXI, AHB, APB and other Management interfaces
• Experience in Synthesis / Understanding of timing concepts in Xilinx/Intel FPGA Implementation is required.
• FPGA Proto-typing experience is a must.
• Experience in design of DDR / USB / PCIe/Ethernet controller or such complex protocols is a plus.
• Experience in Multi Clock designs, Asynchronous interface.

JOB DESCRIPTION

• You will be responsible for IP / sub-system level micro-architecture development and RTL coding.
• Prepare block/sub-system level timing constraints.
• Integrate IP/sub-system.Experience on tools utilized in all phases of ASIC development such as Lint, CDC, Simulation etc. is required.

• Knowledge of low power concepts and experience is a plus

Vacancy expired!