-
ID
#23305539 -
Job type
Contract -
Salary
Depends on Experience -
Source
Nextgen Technologies Inc. -
Date
2021-11-09 -
Deadline
2022-01-08
ASIC Design Verification Engineer
California, San diego, 92121 San diego USAContract
Vacancy expired!
- Define verification architecture, implement verification environment for block level, SoC subsystems, and SOC top-level design that use advanced verification methodologies and meet established content, performance, quality, cost and schedule goals. - Define overall verification strategies, methodologies, and simulation environment
- Work with RTL designers, system architects, and block level verification engineers to develop top-level verification requirements and test plans based on specifications.
- Develop, maintain and publish verification specifications
- Analyze and debug simulation failures
- Generates code coverage and functional coverage report
- Run gate level simulation and debug them. Perform the Constraint Random and Low power Verification, Develop System Verilog Assertions(SVA).
- Minimum of 7-10 year experience in ASIC Verification
- Strong knowledge with ASIC Simulation Tool & Verification Language: all sign-off simulators, Verdi/Siloti
- Fluent in verification languages such as UVM/OVM/RVM/System Verilog, Vera, Verilog
- Experience in writing Test-plans, creating directed and random test cases and low power simulations.
- Should be adept at System Verilog assertions and coverage. Strong scripting skills in Perl, Python, shell etc.
- Strong problem-solving and debug skills to quickly identify and provide solutions under tight schedule pressure
- Education: - B.S. with extensive industry experience
Vacancy expired!
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