Location:San Diego CA/San Jose CA/Austin TX• 5-15 year’s industry experience in a design verification role.• Proficient in System Verilog/UVM/OVM, OOP/C• Knowledge of GPU, experience with Shader, Texture, or Memory System a plus• Experience with code coverage and functional coverage driven verification methodology.• Experience in creating, running and debugging of SystemVerilog/UVM constraint-random Testbench.• Excellent working knowledge of scripting languages such as Python or Perl. Thanks,Tapan
