-
ID
#17811293 -
Job type
Contract -
Salary
Depends on Experience -
Source
SPECTRAFORCE TECHNOLOGIES Inc. -
Date
2021-07-15 -
Deadline
2021-09-13
Design Verification Engineer
California, Menlopark, 94025 Menlopark USAContract
Vacancy expired!
This is
Manisha with Spectraforce Technologies. Spectraforce Technologies is a certified MBE specializing in global contract staffing and payrolling. Spectraforce is an equal opportunity employer, which is a global staffing, consulting and technology solutions company, offering industry-specific solutions to our fortune 500 clients and worldwide corporations. We have opening of Design Verification Engineer in Menlo Park, CA Job Role: Design Verification EngineerDuration: 12 Months Location: Menlo Park, CASummary:As a Design Verification Engineer , you will work with a world-class group of researchers and engineers, and use your digital design and verifications skills to implement the testing infrastructure to validate new core IP implementations and contribute to development and optimization of state of the art vision and sensing algorithms. You will work closely with researchers, architects and designers in creating test bench requirements and test cases for multiple state of the art IPs.Design Verification Engineer Responsibilities:- Work with researchers and architects defining verification methodologies for each of the different core IP.
- Define and track detailed test plans for the different modules and top levels.
- Implement scalable test benches including checkers, reference models, coverage groups in SystemVerilog.
- Keep track of coverage metrics and bugs encountered and fixed.
- Implement self-testing directed and random tests.
- Support post silicon bring up and debug activities.
- Ability to communicate clearly.
- 2+ years of System Verilog OVM/UVM DV experience. HANDS ON EXPERIENCE REQUIRED.
- C, C coding, debugging experience. HANDS ON EXPERIENCE REQUIRED.
- Knowledge of Python, Perl, shell scripting.
- Knowledge with assertions (SVA) or others.
- Knowledge of digital ASICs design flows.
- Experience with low power verification is a PLUS.
- Self-motivated and team player.
- Minimum Bachelor’s degree in Electrical Engineering, Computer Science or equivalent experience
- Preferred Masters in Electrical Engineering or Computer Science.
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