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  • ID
    #55300799
  • Salary
    TBD
  • Source
    Science Applications International Corporation
  • Date
    2026-08-21
  • Deadline
    2026-10-20
 
Full-time

and/or high-speed digital.Schematic entry in a schematic capture software.Experience contributing to engineering documentation for a experience using Vivado for Xilinx hardware (FPGAs, SOCs, MPSOCs etc.) or Quartus for Intel products in Verilog and VHDL.Developing and

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